With the rapid development of the contemporary application-specific integrated circuits, the application of the integrated circuits (chips) has been deep into various fields. In the system design of electronic circuits, the simple system scheme of being comprised of a single chip has been replaced by a scheme of multiple chip sets. The relationship between chips in a single board is closer, and interconnection and exchange visits between chips are inevitable. At the same time, along with the increase in the number of services and the increase in the complexity of the services, the problems of interconnection and exchange visits between chips has gradually become the bottlenecks of the performance of the system, the whole machine and the single board. Therefore, there is an urgent need for a more general, high-speed, simple, and effective interface to complete data exchange and communication operations between the integrated circuits (chips).
The inter-chip interconnection chips may be divided into two types, i.e., parallel interfaces and serial interfaces, or may also be divided into two types according to the order of magnitudes of the transmission speed, i.e., high-speed interfaces and low-speed interfaces. At present, the existing mainstream interfaces comprise UART, SPI, IIC, Serdes, USB, LPT and IDE etc. If the interfaces are divided according to the parallel/serial types, the UART, SPI, IIC, Serdes and USB are transmitted in the serial manner, while the LPT and IDE are parallel transmission interfaces. If the interfaces are divided according to the high-speed/low-speed types, the Serdes, USB and IDE are high-speed interfaces, and the UART, SPI, IIC and LPT belong to low-speed interfaces.
However, the logical complexity of the interfaces is a non-negligible problem when the integrated circuits (chips) are implemented logically. The logical complexity characterizes the scale and area of the hardware circuit, reflects the power consumption level from the side, and embodies the price and investment when the circuit is implemented. The high-speed interfaces typically have higher logical complexity and protocol standard, and also increase the complexity and power consumption level of the chip while obtaining the higher transmission bandwidth. The low-speed transmission interfaces have simple logical design characteristics. However, due to its simple protocol, the Quality of Service (QoS) of the transmission thereof is difficult to be ensured during practical applications.